| 1. |
- Al-Khatib, Iyad, et al.
(författare)
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A Multiprocessor System-on-Chip for Real-Time Biomedical Monitoring and Analysis : Architectural Design Space Exploration
- 2006
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Ingår i: DAC '06. - New York, New York, USA : ACM Press. ; , s. 125-130
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Konferensbidrag (refereegranskat)abstract
- In this paper we focus on MPSoC architectures for human heart ECGreal-time monitoring and analysis. This is a very relevant bio-medicalapplication, with a huge potential market, hence it is an ideal targetfor an application-specific SoC implementation. We investigate asymmetric multi-processor architecture based on STMicroelectronicsVLIW DSPs that process in real-time 12-lead ECG signals. Thisarchitecture improves upon state-of-the-art SoC designs for ECGanalysis in its ability to analyze the full 12 leads in real-time, evenwith high sampling frequencies, and ability to detect heartmalfunction. We explore the design space by considering a number ofhardware and software architectural options.
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| 2. |
- Al Khatib, Iyad, et al.
(författare)
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ECG-BIONET : A global biomedical network for human heart monitoring and analysis: Performance needs of an electrocardiogram Telemedicine platform for medical aid at the point-of-need
- 2006
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Ingår i: 25TH IEEE INTERNATIONAL CONFERENCE ON COMPUTER COMMUNICATIONS. - New York : IEEE. - 9781424402212 ; , s. 3282-3283
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Konferensbidrag (refereegranskat)abstract
- In this paper, we propose a Tele-medicine application platform as a medical aid for patients suffering from Heart malfunction. We focus on heart diseases since they remain by far the major cause of death in the globe. Our solution utilizes the Satellite communication protocol DVB-RCS (Digital Video Broadcast- Return Channel Satellite), Wi-Fi, and the Network-on-Chip (NoC) technology. We utilize the 12-lead ECG biomedical technique to detect heart disorders via the biomedical NoC, which transmits the medical alarm and results via the biomedical network, ECG-BIONET. We do not investigate the DVB-RCS standard or Wi-Fi technology, but rather we try to utilize this technology, and we look at it from a performance point of view for our application by investigating three parameters, namely: delay, packet loss, and reliability. We follow a top down approach by looking at the needs of the application from a performance guarantee for our specific-purpose network.
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| 3. |
- Al Khatib, Iyad, et al.
(författare)
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Hardware/Software architecture for real-time ECG monitoring and analysis leveraging MPSoC technology
- 2007
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Ingår i: Transactions on High-Performance Embedded Architectures and Compilers I. - Berlin, Heidelberg : Springer Berlin Heidelberg. - 9783540715276 ; , s. 239-258
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Konferensbidrag (refereegranskat)abstract
- The interest in high performance chip architectures for biomedical applications is gaining a lot of research and market interest. Heart diseases remain by far the main cause of death and a challenging problem for biomedical engineers to monitor and analyze. Electrocardiography (ECG) is an essential practice in heart medicine. However, ECG analysis still faces computational challenges, especially when 12 lead signals are to be analyzed in parallel, in real time, and under increasing sampling frequencies. Another challenge is the analysis of huge amounts of data that may grow to days of recordings. Nowadays, doctors use eyeball monitoring of the 12-lead ECG paper readout, which may seriously impair analysis accuracy. Our solution leverages the advance in multi-processor system-on-chip architectures, and it is centered on the parallelization of the ECG computation kernel. Our Hardware- Software (HW/SW) Multi-Processor System-on-Chip (MPSoQ design improves upon state-of-the-art mostly for its capability to perform real-time analysis of input data, leveraging the computation horsepower provided by many concurrent DSPs, more accurate diagnosis of cardiac diseases, and prompter reaction to abnormal heart alterations. The design methodology to go from the 12-lead ECG application specification to the final HW/SW architecture is the focus of this paper. We explore the design space by considering a number of hardware and software architectural variants, and deploy industrial components to build up the system.
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| 4. |
- Al-Khatib, Iyad, et al.
(författare)
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Performance Analysis and Design Space Exploration for High-End Biomedical Applications : Challenges and Solutions
- 2007
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Ingår i: Proceedings of the International Conference on Hardware - Software Codesign and System Synthesis. - New York, NY, USA : ACM. - 9781595938244 ; , s. 217-226
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Konferensbidrag (refereegranskat)abstract
- High-end biomedical applications are a good target for specific-purpose system-on-chip (SoC) implementations. Human heart electrocardiogram (ECG) real-time monitoring andanalysis is an immediate example with a large potential market. Today, the lack of scalable hardware platforms limits real-time analysis capabilities of most portable ECG analyzers, and prevents the upgrade of analysis algorithms for better accuracy. Multiprocessor system-on-chip (MPSoC) technology, which is becoming main-stream in the domain of high-performance microprocessors, is becoming attractive even for power-constrained portable applications, due to the capability to provide scalable computation horsepower at an affordable power cost. This paper illustrates one of the first comprehensive HW/SW exploration frameworks to fully exploit MPSoC technology to improve the quality of real-time ECG analysis.
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| 5. |
- Badlund, Per, et al.
(författare)
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An analytical approach for dimensioning mixed traffic networks
- 2007
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Ingår i: NOCS 2007. - 9780769527734 ; , s. 215-215
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Konferensbidrag (refereegranskat)abstract
- We present an analytical method for analyzing and dimensioning a network based communication architecture. The method is based on the classic (a, p) network calculus. We use a TDMA approach for creating logically separated networks which makes statistical methods possible for calculations on Best Effort traffic, and supports implementation of Guaranteed Bandwidth services by using Virtual Circuits with Looped Containers.
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| 6. |
- Chen, Xiaowen, et al.
(författare)
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Speedup Analysis of Data-parallel Applications on Multi-core NoCs
- 2009
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Ingår i: Proceedings of the IEEE International Conference on ASIC (ASICON). - 9781424438686 ; , s. 105-108
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Konferensbidrag (refereegranskat)abstract
- As more computing cores are integrated onto a single chip, the effect of network communication latency is becoming more and more significant on Multi-core Network-onChips (NoCs). For data-parallel applications, we study the model ofparallel speedup by including network communication latency in Amdahl's law. The speedup analysis considers the effect of network topology, network size, traffic model and computation/communication ratio. We also study the speedup efficiency. In our Multi-core NoC platform, a real data-parallel application, i.e. matrix multiplication, is used to validate the analysis. Our theoretical analysis and the application results show that the speedup improvement is nonlinear and the speedup efficiency decreases as the system size is scaled up. Such analysis can be used to guide architects and programmers to improve parallel processing efficiency by reducing network latency with optimized network design and increasing computation proportion in the program.
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| 7. |
- Grange, Matt, et al.
(författare)
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Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh
- 2009
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Ingår i: 2009 IEEE INTERNATIONAL CONFERENCE ON 3D SYSTEMS INTEGRATION. - San Francisco : IEEE conference proceedings. - 9781424445110 ; , s. 345-351
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Konferensbidrag (refereegranskat)abstract
- The physical performance of a 3-Dimensional Network-on-Chip (NoC) mesh architecture employing through silicon vias (TSV) for vertical connectivity is investigated with a cycle-accurate RTL simulator. The physical latency and area impact of TSVs, switches, and the on-chip interconnect is evaluated to extract the maximum signaling speeds through the switches, horizontal and vertical network links. The relatively low parasitics of TSVs compared to the on-chip 2-D interconnect allow for higher signaling speeds between chip layers. The system-level impact on overall network performance as a result of clocking vertical packets at a higher rate through the TSV interconnect is simulated and reported.
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| 8. |
- Grecu, Cristian, et al.
(författare)
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Towards open network-on-chip benchmarks
- 2007
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Ingår i: NOCS 2007. ; , s. 205-212
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Konferensbidrag (refereegranskat)abstract
- Measuring and comparing performance, cost, and other features of advanced communication architectures for complex multi core/multiprocessor systems on chip is a significant challenge which has hardly been addressed so far. This document outlines the top-level view on a system of benchmarks for Networks on Chip (NoC), which intends to cover a wide spectrum of NoC design aspects, from application modeling to performance evaluation and post-manufacturing test and reliability. For performance benchmarking, requirements and features are described for application programs, synthetic micro-benchmarks, and abstract benchmark applications. Then, it proposes ways to measure and benchmark reliability, fault tolerance and testability of the on-chip communication fabric. This paper introduces the main concepts and ideas for benchmarking NoCs in a systematic and comparable way. It will be followed up by a report that will define a benchmark framework and the syntax of interfaces for benchmark programs that will allow the community to build-up a benchmark suite.
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| 9. |
- Guang, Liang, et al.
(författare)
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Adaptive Power Management for the On-Chip Communication Network
- 2006
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Ingår i: DSD 2006. - 0769526098 ; , s. 649-656
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Konferensbidrag (refereegranskat)abstract
- An on-chip communication network is most power efficient when it operates just below the saturation point. For any given traffic load the network can be operated in this region by adjusting frequency and voltage. For a deflective routing network we propose the design of a central controller for dynamic frequency and voltage scaling. Given history information including the load and frequency in the network, the controller adjusts the frequency and voltage such that the network operates just below the saturation point. We provide control mechanisms for continuous and discrete frequency ranges. With a discrete frequency range and taking into account voltage switching delays, we evaluate the control mechanism under stochastic, smoothly varying and very bursty traffic. Experiments demonstrate that adaptive control is very effective in minimizing power consumption at reasonable performance. Compared with a fixed high frequency network, the adaptively controlled network is significantly more power efficient. We compare it to fixed frequency networks, which are either too slow exhibiting unbounded delays, or are dimensioned for the worst case with very high frequency and are very power hungry.
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| 10. |
- Henriksson, Tomas, et al.
(författare)
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Network Calculus Applied to Verification of Memory Access Performance in SoCs
- 2007
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Ingår i: Proceedings of the 2007 IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, ESTIMedia 2007. - 9781424416547 ; , s. 21-26
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Konferensbidrag (refereegranskat)abstract
- SoCs for multimedia applications typically use only one port to off-chip DRAM for cost reasons. The sharing of interconnect and the off-chip DRAM port by several IP blocks makes the performance of a SoC under design hard to predict. Network calculus defines the concept of flow and has been successfully used to analyse the performance of communication networks. We propose to apply network calculus to the verification of memory access latencies. Two novel network elements, packet stretcher and packet compressor, are used to model the SoC interconnect and DRAM controller. We further extend the flow concept with a degree and make use of the peak characteristics of a flow to tighten the bounds in the analysis. We present a video playback case study and show that the proposed application of network calculus allows us to statically verify that all requirements on memory access latency are fulfilled.
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